1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a technique suitable for a package having an LOC (Lead On Chip) structure of a large-scale integrated circuit.
2. Description of the Related Art
The LOC (Lead On Chip) structure allows a relatively small package to accommodate a large semiconductor chip to realize high-density mounting, and is therefore suitable for, e.g., a 16-bit DRAM (Dynamic Random Access Memory). An example of the semiconductor device having the LOC structure is disclosed in, e.g., Japanese Patent Laid-Open No. 4-291950. In the semiconductor device disclosed in this reference, a band-shaped insulating tape 102 with an adhesive applied to its two surfaces is bonded to an inner lead 101 of a lead frame, as shown in FIG. 11. On the other hand, a polyimide film 104 serving as an .alpha.-ray protective film is bonded on a predetermined region of a semiconductor chip 103 where memory cells and their peripheral circuits are formed. As shown in FIG. 11, the upper surface of the polyimide film 104 on the semiconductor chip 103 is bonded and fixed to the inner lead 101 with the insulating tape 102 interposed therebetween, and a bonding pad 105 formed on the semiconductor chip 103 is connected to the inner lead 101 by a bonding wire 106. In the semiconductor device disclosed in Japanese Patent Laid-Open No. 4-291950, the insulating tape 102 has a comb-like shape to prevent voids.
A method of manufacturing the above semiconductor device will be briefly described with reference to FIG. 12. The manufacturing process is divided into a preprocess group before cutting a semiconductor wafer into semiconductor chips and a post-process group after cutting. In the first step of the preprocess group, memory cells and their peripheral circuits are formed on a semiconductor wafer, and a plurality of semiconductor chips are formed on the semiconductor wafer (step S101).
After the prefuse test of the semiconductor chips (step S102), a material film, e.g., a polyimide resin film in this case, serving as an .alpha.-ray protective film is applied to the entire surface of each semiconductor chip (step S103).
The semiconductor wafer on which the protective film is formed is heated at a predetermined temperature (step S104).
A photoresist is applied to the surface of the protective film of each semiconductor chip (step S105), and developed and patterned by photolithography to form an etching mask (step S106). The protective film is anisotropically etched into a shape conforming to the etching mask, and a plurality of openings are formed in the protective film to expose the surfaces of bonding pads formed on the semiconductor chip under the protective film (step S107). The resist mask is removed by ashing using O.sub.2 plasma (step S108). Back grinding (step S109) and laser repair (step S110) are performed, and a full wafer test is performed in the final step of the preprocess group (step S111).
Next, in the first step of the post-process group, dicing is performed to cut the semiconductor wafer into the semiconductor chips (step S112). The following three processes are performed simultaneously with the operation in step S112. An adhesive consisting of a polyimide resin material is applied to the two surfaces of a band-shaped polyimide film as an insulating tape (step S113), the insulating tape is bonded to inner leads (step S114), and the insulating tape is formed into a predetermined shape (step S115).
The inner leads are pressed against the surface of the protective film of each cut semiconductor chip with the insulating tapes interposed therebetween. In this state, the resultant structure is heated to bond and fix the semiconductor chip to the inner leads (step S116). Each semiconductor chip is loaded into a furnace and subjected to post-baking (step S117: this step can be omitted in some cases). The bonding pad in each opening formed in the protective film is connected to a corresponding inner lead by a bonding wire (step S118). Resin molding is performed to cover the entire semiconductor chip (step S119), thereby completing a package.
According to the above-described method, since an adhesive having the same properties as the insulating tape is applied to the two surfaces of the insulating tape, the thickness of the entire insulating tape can be adjusted appropriately, so cracks in the sealing resin and semiconductor chip can be prevented. However, this method requires various processes (steps S113 to S115) for bonding the insulating tape to the inner leads, so the number of processes in manufacturing a lead frame increases, and the processes become cumbersome. In addition, the insulating tape is difficult to handle because it tends to be burred upon cutting and attract foreign objects. Furthermore, since the number of components increases, the cost largely increases.